Microprocessor and Interfacing Essay

Peripherals and Interfacing PIO 8255 The parallel introduce- production carriage chip 8255 is as well as called as programmable peripheral scuttlebutt- step forwardput expression. The Intels 8255 is designed for use with Intels 8-bit, 16-bit and higher capability microprocessors. It has 24 comment/output line of credits which may be individually programmed in two groups of twelve lines each, or three groups of eight lines. The two groups of I/O pins argon named as separate A and Group B. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit fashion and another subgroup of quaternion lines or a 4-bit carriage.Thus Group A contains an 8-bit bearing A along with a 4-bit demeanor. C upper. PIO 8255 The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly, GroupB contains an 8-bit port B, containing lines PB0-PB7 and 4-bit port C with dismount bits PC0- PC3. The port C upper and port C displa ce thr one and only(a) be utilize in combination as an 8-bitport C. Both the port C are assigned the same address. Thus one may have all three 8-bit I/O ports or two 8-bit and two 4-bit ports from 8255. entirely of these ports crumb function independently either as insert or as output ports.This can be achieved by programming the bits of an internal show up of 8255 called as secure word register ( CWR ). PIO 8255 The internal block diagram and the pin configuration of 8255 are shown in fig. The 8-bit entropy motorcoach moderate is viewled by the articulate/write encounter system of logic. The read/write checker logic manages all of the internal and external transfers of both entropy and reign over words. RD, WR, A1, A0 and RESET are the inputs provided by the microprocessor to the READ/ WRITE checker logic of 8255. The 8-bit, 3-state duplex buffer is employ to interface the 8255 internal entropy bus with the external system data bus.PIO 8255 This buffer re ceives or transmits data upon the execution of input or output instructions by the microprocessor. The control words or status information is to a fault transferred through the buffer. The channelise description of 8255 are briefly presented as fol scurvys PA7-PA0 These are eight port A lines that acts as either latched output or buffered input lines depending upon the control word loaded into the control word register. PC7-PC4 Upper nibble of port C lines. They may act as either output latches or input buffers lines. PIO 8255 This port also can be used for generation of handshake lines in fashion 1 or regularity 2. PC3-PC0 These are the confuseder port C lines, other details are the same as PC7-PC4 lines. PB0-PB7 These are the eight port B lines which are used as latched output lines or buffered input lines in the same way as port A. RD This is the input line driven by the microprocessor and should be low to indicate read summons to 8255. WR This is an input line driven by the microprocessor. A low on this line indicates write physical process. PIO 8255 CS This is a chip have line.If this line goes low, it enables the 8255 to respond to RD and WR signals, otherwise RD and WR signal are neglected. A1-A0 These are the address input lines and are driven by the microprocessor. These lines A1-A0 with RD, WR and CS from the following operations for 8255. These address lines are used for addressing any one of the four registers, i. e. three ports and a control word register as given in table below. In vitrine of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.RD 0 0 0 0 RD 1 1 1 1 RD X 1 WR 1 1 1 1 WR 0 0 0 0 WR X 1 CS 0 0 0 0 CS 0 0 0 0 CS 1 0 A1 0 0 1 1 A1 0 0 1 1 A1 X X A0 0 1 0 1 A0 0 1 0 1 A0 X X introduce (Read) cycle port wine A to info bus fashion B to selective information bus mien C to Data bus CWR to Data bus railroad siding (Write ) cycle Data bus to bearing A Data bus to Port B Data bus to Port C Data bus to CWR Function Data bus tristated Data bus tristated Control Word narration PIO 8255. D0-D7 These are the data bus lines those carry data or control word to/from the microprocessor. RESET A logic high on this line clears the control word register of 8255.All ports are set as input ports by default after reset. Block Diagram of 8255 (Architecture) ( cont.. ) 1. 2. 3. 4. It has a 40 pins of 4 groups. Data bus buffer Read Write control logic Group A and Group B controls Port A, B and C Data bus buffer This is a tristate bidirectional buffer used to interface the 8255 to system databus. Data is transmitted or received by the buffer on execution of input or output instruction by the CPU. Control word and status information are also transferred through this unit. Block Diagram of 8255 (Architecture) ( cont.. )Read/Write control logic This unit accepts control signals ( RD, WR ) and also inputs from addr ess bus and issues commands to individual group of control blocks ( Group A, Group B). It has the following pins. a) CS Chipselect A low on this PIN enables the discourse amongst CPU and 8255. b) RD (Read) A low on this pin enables the CPU to read the data in the ports or the status word through data bus buffer. Block Diagram of 8255 (Architecture) ( cont.. ) WR ( Write ) A low on this pin, the CPU can write data on to the ports or on to the control register through the data bus buffer. ) RESET A high on this pin clears the control register and all ports are set to the input personal manner e) A0 and A1 ( Address pins ) These pins in conjunction with RD and WR pins control the selection of one of the 3 ports. Group A and Group B controls These block receive control from the CPU and issues commands to their respective ports. c) Block Diagram of 8255 (Architecture) ( cont.. ) Group A PA and PCU ( PC7 -PC4) Group B PCL ( PC3 PC0) Control word register can only be writt en into no read operation of the CW register is allowed. a) Port A This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3 modes mode 0, mode 1, mode 2. b) Port B This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be programmed in mode 0, mode1. Block Diagram of 8255 (Architecture). c) Port C This has an 8 bit latched input buffer and 8 bit out put latched/buffer. This port can be divided into two 4 bit ports and can be used as control signals for port A and port B. it can be programmed in mode 0. personal manners of Operation of 8255 (cont.. ) These are two basic modes of operation of 8255.I/O mode and Bit Set-Reset mode (BSR). In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits. Under the I/O mode of operation, further there are three modes of operation of 8255, so as to support different types of applications, mode 0, mode 1 and mode 2. Modes of Operation of 8255 (cont.. ) BSR Mode In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control word. The bit to be set or reset is selected by bit select bowling pins D3, D2 and D 1 of the CWR as given in table. I/O Modes a) Mode 0 ( Basic I/O mode ) This mode is also called as basic input/output mode. This mode provides simple input and output capabilities using each of the three ports. Data can be precisely read from and written to the input and output ports respectively, after appropriate initialisation. D3 0 0 0 0 1 1 1 1 D2 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 submited bits of port C D0 D1 D2 D3 D4 D5 D6 D7 BSR Mode CWR formatting PA 8 2 5 5 PCU PCL PA6 PA7 PC4 PC7 PC0-PC3 PB PB0 PB7 8 2 5 5 PA PCU PCL PB PA PC PB0 PB7 All railroad siding Port A and Port C performing as O/P. Port B acting as I/PMode 0 Modes of Operation of 8255 (cont.. ) 1. The salient features of this mode are as listed below Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upper and lower ) are available. The two 4-bit ports can be combinedly used as a third 8-bit port. Any port can be used as an input or output port. end product ports are latched. stimulation ports are not latched. A maximum of four ports are available so that overall 16 I/O configuration are possible. All these modes can be selected by programming a register internal to 8255 known as CWR. 2. 3. 4. Modes of Operation of 8255 (cont.. The control word register has two formats. The first format is valid for I/O modes of operation, i. e. modes 0, mode 1 and mode 2 while the second format is valid for bit set/reset (BSR) mode of operation. These formats are shown in following fig. D7 1 D6 X D5 X D4 X D3 D2 D1 D0 0- Reset 0-for BSR mode Bit select flags D3, D2, D1 are from 000 to 111 for bits PC0 TO PC71- Set I/O Mode Control Word Register Format and BSR Mode Control Word Register Format PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA4 PA5 PA6 PA7 WR Reset D0 D1 D2 D3 D4 D5 D6 D7 Vcc PB7 PB6 PB5 PB4 PB3 8255A 8255A Pin Configuration = D0-D7 CS RESET 8255A A0 A1 RD PA0-PA7 PC4-PC7 PC0-PC3 PB0-PB7 Vcc WR GND Signals of 8255 3 Group A control 1 D0-D7 Data bus soften 8 bit int data bus 4 Group A Port A(8) PA0-PA7 Group A Port C upper(4) Group B Port C Lower(4) PC7-PC4 PC0-PC3 2 RD WR A0 A1 RESET CS Block Diagram of 8255 READ/ WRITE Control Logic Group B control PB7-PB0 Group B Port B(8) D7 D6 D5 Mode for Port A D4 PA D3 PC U D2 Mode for PB D1 PB D0 PC LMode Set flag 1- active 0- BSR mode Group A 1 Input PC u 0 Output 1 Input PA 0 Output 00 mode 0 Mode 01 mode 1 Select of PA 10 mode 2 Group B PCL PB Mode Select 1 Input 0 Output 1 Input 0 Output 0 mode- 0 1 mode- 1 Control Word Format of 8255 Modes of Operation of 8255 (cont.. ) b) Mode 1 ( Strobed input/output mode ) In this mo de the handshaking control the input and output action of the specified port. Port C lines PC0-PC2, provide strobe or handshake lines for port B. This group which includes port B and PC0-PC2 is called as group B for Strobed data input/output. Port C lines PC3-PC5 provide strobe lines for port A.This group including port A and PC3-PC5 from group A. Thus port C is utilized for generating handshake signals. The salient features of mode 1 are listed as follows Modes of Operation of 8255 (cont.. ) 1. 2. 3. 4. Two groups group A and group B are available for strobed data transfer. Each group contains one 8-bit data I/O port and one 4-bit control/data port. The 8-bit data port can be either used as input and output port. The inputs and outputs both are latched. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and PC3-PC5 are used to generate control signals for port A. he lines PC6, PC7 may be used as independent data lines. Modes of Operation of 8255 (cont.. ) The control signals for both the groups in input and output modes are explained as follows Input control signal definitions (mode 1 ) STB( Strobe input ) If this lines falls to logic low level, the data available at 8-bit input port is loaded into input latches. IBF ( Input buffer full ) If this signal rises to logic 1, it indicates that data has been loaded into latches, i. e. it works as an acknowl pungencyment. IBF is set by a low on STB and is reset by the rising edge of RD input.Modes of Operation of 8255 (cont.. ) INTR ( Interrupt request ) This active high output signal can be used to burst the CPU whenever an input thingmabob requests the service. INTR is set by a high STB pin and a high at IBF pin. INTE is an internal flag that can be controlled by the bit set/reset mode of either PC4 (INTEA) or PC2(INTEB) as shown in fig. INTR is reset by a falling edge of RD input. Thus an external input device can be request the service of the processor by putting the data on the bus and displace the strobe signal. Modes of Operation of 8255 (cont.. Output control signal definitions (mode 1) OBF (Output buffer full ) This status signal, whenever falls to low, indicates that CPU has written data to the specified output port. The OBF tack will be set by a rising edge of WR signal and reset by a low expiration edge at the ACK input. ACK ( Acknowledge input ) ACK signal acts as an acknowledgement to be given by an output device. ACK signal, whenever low, informs the CPU that the data transferred by the CPU to the output device through the port is received by the output device.Modes of Operation of 8255 (cont.. ) INTR ( Interrupt request ) Thus an output signal that can be used to interrupt the CPU when an output device acknowledges the data received from the CPU. INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR input. The INTEA and INTEB flags are controlled by the bit set-reset mode of PC 6and PC2 respectively. 1 0 1 0 Input control signal definitions in Mode 1 1/0 X X X 1 X X X X 1 1 X D7 D6 D5 D4 D3 D2 D1 D0 1 Input 0 Output For PC6 PC7 PA0 PA7 INTEA PC4 PC5 STBA IBFA D7 D6 D5 D4 D3 D2 D1 D0PB0 PB7 INTEB PC 2 PC1 STBB IBFB PC3 RD PC6 PC7 INTRA I/O PC0 INTR A Mode 1 Control Word Group A I/P RD Mode 1 Control Word Group B I/P STB IBF INTR RD DATA from Peripheral Mode 1 Strobed Input Data Transfer WR OBF INTR ACK Data OP to Port Mode 1 Strobed Data Output Output control signal definitions Mode 1 1 0 1 0 1/0 X X X 1 X X X X 1 0 X D7 D6 D5 D4 D3 D2 D1 D0 1 Input 0 Output For PC4 PC5 PA0 PA7 INTEA PC7 PC6 OBF ACKA D7 D6 D5 D4 D3 D2 D1 D0 PB0 PB7 INTEB PC PC2 1 OBFB ACKB PC3 WR PC4 PC5 PC0 INTRA I/O INTRB Mode 1 Control Word Group AMode 1 Control Word Group B Modes of Operation of 8255 (cont.. ) Mode 2 ( Strobed bidirectional I/O ) This mode of operation of 8255 is also called as strobed bidirectional I/O. This mode of operation provides 8255 with an additional features for communicating w ith a peripheral device on an 8-bit data bus. Handshaking signals are provided to maintain proper data flow and synchronization between the data transmitter and receiver. The interrupt generation and other functions are similar to mode 1. In this mode, 8255 is a bidirectional 8-bit port with handshake signals.The RD and WR signals decide whether the 8255 is going to operate as an input port or output port. Modes of Operation of 8255 (cont.. ) 1. 2. 3. 4. 5. The Salient features of Mode 2 of 8255 are listed as follows The single 8-bit port in group A is available. The 8-bit port is bidirectional and additionally a 5-bit control port is available. Three I/O lines are available at port C. ( PC2 PC0 ) Inputs and outputs are both latched. The 5-bit control port C (PC3-PC7) is used for generating / accepting handshake signals for the 8-bit data transfer on port A.Modes of Operation of 8255 (cont.. ) Control signal definitions in mode 2 INTR (Interrupt request) As in mode 1, this con trol signal is active high and is used to interrupt the microprocessor to ask for transfer of the nigh data byte to/from it. This signal is used for input ( read ) as well as output ( write ) operations. Control Signals for Output operations OBF ( Output buffer full ) This signal, when falls to low level, indicates that the CPU has written data to port A. Modes of Operation of 8255 (cont.. ) ACK ( Acknowledge ) This control input, when falls to logic low level, acknowledges that the previous data byte is received by the destination and next byte may be sent by the processor. This signal enables the internal tristate buffers to send the next data byte on port A. INTE1 ( A flag associated with OBF ) This can be controlled by bit set/reset mode with PC6 . Control signals for input operations STB (Strobe input ) A low on this line is used to strobe in the data into the input latches of 8255. Modes of Operation of 8255 (cont.. ) IBF ( Input buffer full ) When the data is loaded into input buffer, this ignal rises to logic 1. This can be used as an acknowledge that the data has been received by the receiver. The waveforms in fig show the operation in Mode 2 for output as well as input port. Note WR must occur before ACK and STB must be activated before RD. WR OBF INTR ACK STB IBF Data bus RD Mode 2 Bidirectional Data Transfer Data from 8085 Data towards 8255 Modes of Operation of 8255 (cont.. ) The following fig shows a schematic diagram containing an 8-bit bidirectional port, 5-bit control port and the relation of INTR with the control pins. Port B can either be set to Mode 0 or 1 with port A( Group A ) is in Mode 2. Mode 2 is not available for port B. The following fig shows the control word. The INTR goes high only if either IBF, INTE2, STB and RD go high or OBF, INTE1, ACK and WR go high. The port C can be read to know the status of the peripheral device, in terms of the control signals, using the normal I/O instructions. D7 1 D6 1 D5 X D4 X D3 X D2 1/0 D1 1/0 D0 1/0 1/0 mode Port A mode 2 Port B mode 0-mode 0 1- mode 1 PC2 PC0 1 Input 0 Output Port B 1- I/P 0-O/P Mode 2 control word PC3 PA0-PA7 INTR INTE 1 PC7 PC6 OBF ACK STB IBF 3 I/O INTE 2 RD WR PC4 PC5 Mode 2 pins